Memory devices are typically provided as internal, semiconductor, integrated circuits in computers or other electronic devices. There are many different types of memory including random-access memory (RAM), read only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), and flash memory.
Flash memory devices have developed into a popular source of non-volatile memory for a wide range of electronic applications. Flash memory devices typically use a one-transistor memory cell that allows for high memory densities, high reliability, and low power consumption. Common uses for flash memory include personal computers, personal digital assistants (PDAs), digital cameras, and cellular telephones. Program code and system data such as a basic input/output system (BIOS) are typically stored in flash memory devices for use in personal computer systems.
As the performance and complexity of electronic systems increase, the requirement for additional memory in a system also increases. However, in order to continue to reduce the costs of the system, the parts count must be kept to a minimum. This can be accomplished by increasing the memory density of an integrated circuit.
Memory density can be increased by using multiple level cells (MLC) instead of single level cells (SLC). MLC memory can increase the amount of data stored in an integrated circuit without adding additional cells and/or increasing the size of the die. The MLC method stores two or more data bits in each memory cell.
FIG. 1 illustrates a typical prior art SLC NAND memory cell array. This figure shows a 16 k bit line and 32 word line memory array as used in a typical 2 kilobyte (kB) memory block. As can be seen, the array is comprised of word lines WL0-WL31 and bit lines BL0-BL16383. Select gate drain (SGD) transistors 101, 102 and select gate source (SGS) transistors 104, 105 are used on each end of each bit line to enable selective access to the array. A source line 100 is coupled to the source end of the serial bit lines.
Each word line of the SLC array is considered to be a page of data. For example, WL0 can be considered to be page 0 with 2 kB of data. WL1 is then page 1. This continues up to WL31 that is labeled page 31.
FIG. 2 illustrates a typical prior art MLC NAND memory cell array. This figure shows basically the same architecture as the SLC array including bit lines BL0-BL16383, WL0 -WL31, the SGD transistors 201, 202, SGS transistors 204, 205, and the source line 200. However, the MLC memory array is comprised of 63 pages of data since it has two bits for each memory cell.
Each word line WL0-WL31 of the MLC array is comprised of two pages of data. For example, WL0 is page 0 and page 1 that is equal to 4 kB of data. This continues up to WL31 that is comprised of page 62 and page 63. In other words, the lower pages are even pages page 0, page 2, . . . page 62. The upper page data are the odd pages page 1, page 3, . . . page 63. During a programming operation, the memory controller typically first sends the lower page data for programming then the upper page data is programmed.
A multilevel cell has multiple threshold voltage (Vt) windows that each indicates a different state. FIG. 3 illustrates a typical MLC Vt distribution for lower page and upper page data. Multilevel cells take advantage of the analog nature of a traditional flash cell by assigning a bit pattern to a specific voltage range stored on the cell. This technology permits the storage of two or more bits per cell, depending on the quantity of voltage ranges assigned to the cell.
FIG. 3 shows that the lower page of data Vt is comprised of one of two states only (i.e., “11” or “10”) where the right-most bit is considered to be the lower page of data. In such a distribution, there is no need for a tight “10” state since there is enough of a Vt difference between the “11” state and the “10” state. The “11” state is typically referred to as the erased state.
The rLP voltage indicated along the Vt axis is the lower page read bias that is applied to the selected word line. An unselected word line voltage is approximately 5.5V to bypass the even upper cell states. The rLP voltage is typically around 0.5V.
The lower distribution of FIG. 3 is the upper page cell Vt distribution. The upper page data is written to the cells already programmed with the lower page of data. The arrows from the lower page Vt distribution to the upper page Vt distribution shows the possible changes in state. For example, the erase state, “11”, can become a logical “11” 301 after a logical “1” is programmed into the upper page of data or it can become a logical “01” 302 after the upper page of data is programmed as a logical “0”. The lower page programmed state of “10” can either become a logical “00” 305 after the upper page of data is programmed as a logical “0” state or it can become a “10” 306 after the upper page is programmed as a logical “1”.
Since there are now four states in the lower distribution of FIG. 3, a tighter cell Vt distribution is required. The voltage r00 is illustrated along the Vt axis. The r00 voltage is the voltage used to bias the word lines in order to read the lower data when the upper data has been written. Typically, r00 is 1.3V.
For the lower page reading of an MLC state, the upper page data is written for the selected word line. For the lower page reading of an SLC state, the upper page data is not written for the selected word line. Therefore, it is necessary to have information available to determine whether the selected word line has had the upper page cell data written.
MLC flash memory devices typically use flag data stored in a flag data cell to indicate to the internal controller inside the flash memory whether the upper page is written or not for the selected word line. For the lower page reading case, the flag data is used by the internal controller inside the flash memory to decide the internal read algorithm. If the flag data shows the upper page is not written, only the lower page is written so that the lower page read needs to be executed further to read correct data. If the flag data shows the upper page data is not written, the already read data is the correct data. Therefore, there is no need for a further read operation. Reading the flag data can cause a data cache busy indicator to indicate, during worst case conditions, that the cache is busy during a time when a lower page read voltage needs to be generated in an MLC device. This can cause a conflict during lower page access in an MLC device.
For the reasons stated above, and for other reasons stated below that will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for an improved data cache read performance in a multilevel cell memory device.